1. Technical Field
Embodiments described herein are related to the field of capacitors used in semiconductor devices. More particularly, these embodiments relate to methods for implementing capacitors within an analog-to-digital converter circuit.
2. Description of the Related Art
An array of capacitors may be used as part of a digital-to-analog converter (DAC) circuit. DAC circuits are used in some analog-to-digital converter (ADC) architectures, such as successive approximation register (SAR) ADCs, for example. Small, accurately matched, capacitors are desirable for a DAC used in a SAR ADC to produce an accurate digital value representing a given analog signal input. SAR ADCs are used in some integrated circuits (ICs) designs, such as some system-on-a-chip (SoC) designs.
Some ICs are manufactured in a semiconductor fabrication process that includes multiple layers of metal interconnects which are used to connect various circuit devices to each other to create various functional blocks that may be found in a given IC, including DACs and ADCs. The metal layers are separated from each other by a non-conductive layer, such as silicon dioxide (i.e., glass, or referred to herein as an “oxide layer” or simply “oxide”). Capacitors may be constructed from these multiple metal layers by processing each metal layer in a given region into specific shapes, such as wires and plates, and then connecting the various wires and plates to form a capacitor.
To use capacitors in an IC design, a basic building block may be utilized, referred to herein as a unit capacitor cell. A unit capacitor cell in a given IC design may have a unit value of capacitance and building capacitors with a capacitance greater than the unit value requires combining two or more unit capacitor cells, allowing capacitors to be designed with capacitance values equal to an integer multiple of the unit value.
In some IC designs, however, some circuits may benefit from a capacitor whose value that is not an integer multiple of a unit value of a unit capacitor cell. A method of designing and replicating a capacitor cell with capacitance less than one unit value is desired.